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Vulnerability record · CVE-2026-62430 · published 28 July 2026

CVE-2026-62430: Race condition vulnerability

Accesses to the CMOS memory contents are done using an indirect IO port pair. Therefore Xen needs to cache the guest chosen index, and one of the usages of the index didn't take the necessary locking to avoid concurrent changes. As a result, a guest could change the index after it being checked, causing a subsequent out-of-bound read access to the contents of an array.

7.5 CVSS 3.1 High EPSS 0.38% · top 70.7% CWE-362 · Race condition Deferred
7.5CVSS 3.1 base score
0.38%EPSS exploitation probability, 30 days
NoNot in CISA KEV
0Affected product versions listed by NVD
3References
28 Jul 2026Last modified by NVD

Description

Accesses to the CMOS memory contents are done using an indirect IO port pair. Therefore Xen needs to cache the guest chosen index, and one of the usages of the index didn't take the necessary locking to avoid concurrent changes. As a result, a guest could change the index after it being checked, causing a subsequent out-of-bound read access to the contents of an array.

CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:N

References

LinkTags
https://xenbits.xenproject.org/xsa/advisory-503.html
http://www.openwall.com/lists/oss-security/2026/07/28/19
http://xenbits.xen.org/xsa/advisory-503.html

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Source: NIST National Vulnerability Database (record CVE-2026-62430), CISA KEV, FIRST EPSS (scores of 2026-09-26). This page is refreshed as NVD updates the record.