Vulnerability record · CVE-2026-23554 · published 23 March 2026
CVE-2026-23554: Xen toctou race condition vulnerability
Xen · Xen
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
Description
The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
Affected products
1 vulnerable configurations from NVD's CPE data, grouped by vendor and product.
References
| Link | Tags |
|---|---|
| https://xenbits.xenproject.org/xsa/advisory-480.html | PatchVendor Advisory |
| http://www.openwall.com/lists/oss-security/2026/03/17/6 | Mailing ListPatchThird Party Advisory |
| http://xenbits.xen.org/xsa/advisory-480.html | PatchVendor Advisory |
Track CVE-2026-23554 inside VULONE
Watch it alongside the ransomware crews, C2 infrastructure and forum chatter that reference it, query it through the API and pull it into your SIEM over TAXII.
Related vulnerabilities
Same products first, then exploited flaws of the same weakness class.
Source: NIST National Vulnerability Database (record CVE-2026-23554), CISA KEV, FIRST EPSS (scores of 2026-09-28). This page is refreshed as NVD updates the record.